preliminary preliminary ds-cpc3730-r00c 1 cpc3730 n-channel depletion-mode fet rohs 2002/95/ec e 3 pb part # description CPC3730CTR sot-89 (1000/reel) bv dsx / bv dgx r ds(on) (max) i dss (min) package 350v p 30 ? 140ma sot-89 applications features description ordering information package pinout ? ignition modules ? normally-on switches ? solid state relays ? converters ? telecommunications ? power supply ? low r ds(on) at cold temperatures ? r ds(on) 30 ? max. at 25oc ? high input impedance ? high breakdown voltage: 350v p ? low v gs(off) voltage: -1.6 to -3.9v ? small package size: sot-89 the cpc3730 is an n-channel, depletion mode, field effect transistor (fet) that utilizes clare?s proprietary third-generation vertical dmos process. the third-generation process realizes world class, high voltage mosfet performance in an economical silicon gate process. our vertical dmos process yields a robust device, with high input impedance, for use in high power applications. the cpc3730 is a highly reliable fet device that has been used extensively in clare?s solid state relays for industrial and telecommunications applications. this device excels in power applications requiring low drain-source resistance, particularly in cold environments such as automotive ignition modules. the cpc3730 offers a low, 30 ? maximum, on-state resistance at 25oc. the cpc3730 has a minimum breakdown voltage of 350v p , and is available in an sot-89 package. as with all mos devices, the fet structure prevents thermal runaway and thermal-induced secondary breakdown. (sot-89) g d s d circuit symbol d s g
preliminary 2 r00c cpc3730 absolute maximum ratings are stress ratings. stresses in excess of these ratings can cause permanent damage to the device. functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. absolute maximum ratings @ 25oc electrical characteristics @ 25oc (unless otherwise noted) parameter ratings units drain-to-source voltage 350 v p gate-to-source voltage 20 v p total package dissipation 1.6 1 w operational temperature -55 to +125 o c storage temperature -55 to +125 o c 1 mounted on fr4 board 1"x1"x0.062" package i d (continuous) i d (pulsed) power dissipation @t a =25 o c ? jc o c/w i dr i drm sot-89 140ma 600ma 1.6w 1 15 140ma 600ma 1 mounted on fr4 board 1"x1"x0.062" thermal characteristics parameter symbol conditions min typ max units drain-to-source breakdown voltage bv dsx v gs = -5v, i d =100a 350 - - v p gate-to-source off voltage v gs(off) i ds = 15v, i d =1ma -1.6 - -3.9 v change in v gs(off) with temperatures dv gs(off) /dt v ds = 15v, i d =1ma - - 4.5 mv/ o c gate body leakage current i gss v gs =20v, v ds =0v - - 100 na drain-to-source leakage current i d(off) v gs = -5v, v ds =max rating - - 1 ? a v gs = -5v, v ds =280v, t a =125oc - - 1 ma saturated drain-to-source current i dss v gs = 0v, v ds =15v 140ma - - ma static drain-to-source on-state resistance r ds(on) v gs = 0v, i d =140ma - - 30 ? change in r ds(on) with temperatures dr ds(on) /dt v gs = 0v, i d =140ma - - 1.1 %/ o c forward transconductance g fs i d = 100ma, v ds = 10v 150 - - m input capacitance c iss v gs = -5v v ds = 25v f= 1mhz - 100 200 pf common source output capacitance c oss 20 100 reverse transfer capacitance c rss 580 turn-on delay time t d(on) v dd = 25v i d = 150ma v gs = 0v to -10v r gen = 50 ? - 20 -ns rise time t r 10 turn-off delay time t d(off) 20 fall time t f 50 source-drain diode voltage drop v sd v gs = -5v, i sd = 150ma - 0.6 1.8 v ? switching waveform & test circuit 90% 10% 90% 90% 10% 10% pulse generator v dd r l output d.u.t. t (on) t d(on) t (off) t d(off) t f t r input input output 0v v dd r gen 0v -10v
cpc3730 preliminary 3 r00c performance data* *the performance data shown in the graphs above is typical of device performance. for guaranteed parameters not indicated in t he written speci? cations, please contact our application department. output characteristics (t a =25oc) v ds (v) i d (ma) 0 1 2 3 4 5 150.0 135.0 120.0 105.0 90.0 75.0 60.0 45.0 30.0 15.0 0 6 v gs =-1.0 v gs =-2.0 v gs =-1.5 v gs =0.0 transfer characteristics (v ds =5v) v gs (v) i d (ma) -3.0 -2.5 -2.0 -1.5 -1.0 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0 +125 o c -40 o c +25 o c v gs(off) vs. temperature (v ds =10v, i d =1ma) -40 0 40 80 120 temperature (oc) v gs(off) (v) 0 -0.4 -0.8 -1.2 -1.6 -2.0 -2.4 -3.0 r on vs. temperature (v gs =0v, i d =80ma) -40 0 40 80 120 42.0 36.0 30.0 24.0 18.0 12.0 6.0 0 temperature (oc) r on ( ) power dissipation vs. ambient temperature power dissipation (w) 0 20 40 60 80 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 100 120 140 temperature (oc) v ds (v) i d (a) 0 10 100 1000 1.0 0.1 0.001 0.0001 maximum rated safe operating area at 25 o c on-resistance vs. drain current (v gs =0v) i d (a) 0.00 0.04 0.08 50 45 40 35 30 25 20 15 10 5 0 0.12 0.16 0.2 r on ( ) capacitance vs. drain-source voltage (v gs =-5v) v ds (v) c (pf) 0 10 20 160 140 120 100 80 60 40 20 0 30 40 v iss v rss v oss
preliminary 4 r00c cpc3730 manufacturing information moisture sensitivity all plastic encapsulated semiconductor packages are susceptible to moisture ingression. clare classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, ipc/jedec j-std-020 , in force at the time of product evaluation. we test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. this product carries a moisture sensitivity level (msl) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard ipc/jedec j-std-033 . device moisture sensitivity level (msl) rating cpc3730c msl 1 esd sensitivity this product is esd sensitive , and should be handled according to the industry standard jesd-625 . reflow profile this product has a maximum body temperature and time rating as shown below. all other guidelines of j-std-020 must be observed. device maximum temperature x time cpc3730c 260oc for 30 seconds board wash clare recommends the use of no-clean flux formulations. however, board washing to remove flux residue is acceptable. since clare employs the use of silicone coating as an optical waveguide in many of its optically isolated products, the use of a short drying bake may be necessary if a wash is used after solder reflow processes. chlorine-based or fluorine-based solvents or fluxes should not be used. cleaning methods that employ ultrasonic energy should not be used. rohs 2002/95/ec e 3 pb
clare, inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publica tion and reserves the right to make changes to specifications and product descriptions at any time without notice. neither circuit patent licenses nor indemnity are expressed or implied. except as set forth in clare?s standard terms and conditions of sale, clare, inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products incl uding, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. the products described in this document are not designed, intended, authorized or warranted for use as components in systems in tended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of clare?s product may result in direct physical harm, i njury, or death to a person or severe property or environmental damage. clare, inc. reserves the right to discontinue or make changes to its products at any time without notice. specification: ds-cpc3730-r00c ?copyright 2011, clare, inc. all rights reserved. printed in usa. 5/24/2011 for additional information please visit our website at: www.clare.com cpc3730 5 preliminary mechanical dimensions dimensions mm min / mm max (inches min / inches max) 2.286 / 2.591 (0.090 / 0.102) 3.937 / 4.242 (0.155 / 0.167) 1.397 / 1.600 (0.055 / 0.063) 0.356 / 0.432 (0.014 / 0.017) 1.626 / 1.829 (0.064 / 0.072) r 0.254 (r 0.010) 0.889 / 1.194 (0.035 / 0.047) 0.356 / 0.483 (0.014 / 0.019) 0.432 / 0.559 (0.017 / 0.022) 4.394 / 4.597 (0.173 / 0.181) 1.422 / 1.575 (0.056 / 0.062) 2.921 / 3.073 (0.115 / 0.121) 0.60 (0.024) typ 3 1.40 (0.055) 2.70 (0.107) 1.90 (0.075) 1.90 (0.074) 45o 5.00 (0.197) 50o pcb land pattern note: tape dimensions not shown comply with jedec standard eia-481-2 dimensions mm (inches) top cover tape embossment embossed carrier 177.8 dia (7.00 dia) top cover tape thickness 0.102 max (0.004 max) k 0 =1.90 0.10 (0.075 0.004) p=8.00 0.10 (0.315 0.004) a 0 =4.91 0.10 (0.193 0.004) b 0 =4.52 0.10 (0.178 0.004) w=12.00 0.30 (0.472 0.012) cpc3730c cpc3730c tape & reel
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